Senior Principal Engineer, RFIC Design

Join Kyocera International, Inc.

We're hiring a Senior Principal Engineer, RFIC Design at our San Diego, CA location!

Join a stable, long-term opportunity where your work matters. We're hiring a Senior Principal Engineer, RFIC Design to support production and ensure high-quality output in a fast-paced manufacturing setting.

Pay Range - $155,000.00 to $348,000.00 annually (Actual base pay based on factors such as relevant experience, education, market, qualifications, and skills.)

With nearly 80,000 employees globally, Kyocera is a leading manufacturer of high-tech ceramics in various industries, including aerospace, automotive, Medical applications, and semiconductor processing. Our innovative materials are found in everything from smartphones to space shuttles! Check out our profile video!

Look at these PERKS!

• Competitive pay, benefits, and hours
• 120 hours of vacation accrued per year to start (that's 3 weeks/year for regular 8-hour shifts!)
• 10 Paid Holidays per year
• 401(k) with company match
• Pension
• Medical, dental, and vision insurance
• Flexible Spending Account (FSA)
• Employee Assistance Program
• Flexible schedules
• Tuition reimbursement

We have a long-tenured staff (many with over 30 years of service!), a vital company mission, and an excellent benefits package that includes medical, dental, vision, life insurance, paid time off to volunteer, paid leave options, tuition reimbursement, an employer-paid Pension and a 401(k) with both Roth and a healthy company match. Our larger locations also feature onsite gyms, walking tracks, exercise rooms, and employee gardens!

We strive to have a diverse workforce from all backgrounds, including minorities, women, and veterans, who bring their experience to support the innovation and quality that Kyocera is known for.

Kyocera International, Inc. also has a robust corporate culture and philosophy based on the experiences and writings of our founder, Dr. Kazuo Inamori, which you can learn more about here: https://global.kyocera.com/inamori/philosophy/. Our company motto is "Do the right thing as a human being," and we try to use that motto constantly in our decision-making.

Exempt: Yes

Leads the development of high-performance RF and mmWave transceiver SoCs, with primary emphasis on SATCOM and radar and application to 5G. The role spans architecture through production across transmitter, receiver, frequency-synthesis, mixed-signal, beamforming, calibration, control, and power-management functions. Experience delivering multiple generations of SATCOM and/or radar products is a strong plus.

RESPONSIBILITIES

* Lead the architecture, design, integration, verification, characterization, and commercialization of complete RF/mmWave transceiver ICs and modules for SATCOM terminals and payloads, radar sensors, and 5G systems.

* Perform hands-on schematic design, simulation, layout, extraction, EM analysis, verification, integration, and silicon validation of critical RF, analog, and mixed-signal blocks and modules.

* Translate system requirements into transceiver, synthesizer, mixed-signal, and array specifications and budgets; allocate margin across IC, package, PCB, antenna, process, voltage, temperature, aging, and calibration, and close performance gaps through analysis and measurement.

* Provide technical leadership for SATCOM and radar front ends, phased arrays, and beamformers; partner with systems, modem, antenna, and signal-processing teams on waveforms, frequency planning, interference, coexistence, calibration, and system performance.

* Guide RFIC-package-PCB-antenna co-design and lead design, layout, EM, mixed-signal, verification, and data reviews; establish requirements traceability and signoff criteria while mentoring engineers and resolving cross-functional issues.

* Partner with Product, Test, Applications, Firmware, Digital, Software, and Manufacturing teams on characterization, ATE, observability, built-in self-test, loopback and diagnostic modes, trims, guard bands, qualification, and simulation-to-bench-to-ATE-to-OTA correlation.

* Lead silicon bring-up, system integration, customer demonstrations, root-cause analysis, field-failure resolution, yield improvement, and production ramp.

* Influence product and technology roadmaps, platform reuse, technical risk decisions, and intellectual property for future SATCOM, radar, and 5G products.

QUALIFICATIONS

* Ph.D. or M.S. in Electrical Engineering or a related field, with 15+ years of RF/analog/mixed-signal IC design experience and demonstrated technical leadership of complex RFIC products and programs.

* Deep hands-on experience with complete RF/mmWave transceiver and phased-array architectures, with broad familiarity across transmitter and receiver chains, PLLs/VCOs and LO distribution, mixers, LNAs, PAs and drivers, VGAs, phase shifters, data-converter or baseband interfaces, calibration and digital control, passives, biasing, protection, and power management.

* Demonstrated success delivering RF/mmWave transceiver, phased-array, or RF module products from requirements and architecture through tapeout, lab and OTA validation, qualification, production test, yield improvement, and production ramp. Direct experience with multiple generations of SATCOM and/or radar products is preferred.

* SATCOM: Strong experience with terminal or payload transceiver and phased-array architectures, link budgets, EIRP, G/T, receiver sensitivity and blocking, transmitter linearity and emissions, antenna and polarization concepts, modem/RF interactions, frequency planning, interference and coexistence, calibration, environmental constraints, and conducted and OTA validation. Familiarity with customer/operator requirements and applicable spectrum regulations is desirable.

* Radar: Strong experience with FMCW and pulse-radar transceiver and phased-array architectures, waveform and chirp generation, phase noise and spurs, timing and synchronization, phase coherence, receiver sensitivity and dynamic range, Tx-to-Rx leakage and isolation, Range/Doppler/Angle performance, clutter and interference, beamforming and OTA validation.

* Strong command of transceiver, synthesizer, mixed-signal, and array tradeoffs, including noise figure, blocking, gain and dynamic range, output power and efficiency, linearity, EVM and emissions, phase noise and spurs, settling and chirp linearity, isolation, data-converter performance, beam accuracy, calibration, power, thermal performance, reliability, and production variation.

* Deep understanding of RFIC implementation in CMOS and SOI, including device limits, self-heating, safe operating area, passive/EM structures, layout, packaging, and reliability.

* Proficiency with RFIC, circuit, EM, statistical, electrothermal, mixed-signal, and behavioral modeling tools, including Cadence Virtuoso/Spectre and EMX, ADS and HFSS. MATLAB, Python, Verilog-A, Verilog, or SystemVerilog experience is beneficial.

* Strong RF/mmWave laboratory, analytical, communication, and leadership skills, including silicon debug, simulation-to-measurement correlation, technical reviews, mentoring, risk management, and clear communication with engineering teams, customers, and senior management.